Welcome to the second to last lecture on architectural supercomputers.

Before we begin with the actual lecture, I would like to thank you guys for the evaluation.

We will discuss that tomorrow in detail, but I'm very happy that eight people did submit

the evaluation.

Oh, it's even nine people right now.

Eight people, yeah.

If we include the cameraman, then nine.

So last time, we did stop after a brief historical overview

of GPUs and how the development went,

basically from entertainment devices

to programmable devices, which can be used

for actual scientific computations.

I would like now to continue with a more scientific view on GPUs,

not so much a historical view.

Who of you knows Michael Flynn's taxonomy?

Okay, at least some of you.

Basically Flynn tried to classify computers

and also parallel computers.

So his taxonomy basically distinguishes

how many instruction streams and data streams a machine has.

For instance, a classic single core, non-vectorized,

non-simultaneous multi-threading enabled CPU

would be a single instruction, single data machine.

Probably the microcontroller in my toaster is a SysD device.

SIMD, SIMD is probably the most used abbreviation.

SIMD stands for single instruction multiple data,

and that's for instance used for describing

vector instruction sets.

For instance, if you have SSE or AVX in your CPU,

then you could say that core is a SIMD device.

Although I have to say that this MD

originally had a different meaning.

Originally this was really,

it referred to multiple data streams,

and classic short vector instruction sets we have in,

for instance, the x86 CPUs,

don't have multiple data streams for their vectorized,

for the vectorized instructions.

They typically assume that you're reading a large chunk,

for instance half a cache line,

depending on how large your vector word is,

and they say this is our multiple data,

but it's not multiple data streams.

Originally SIMD did refer, for instance, to vector CPUs,

where they could use different offsets

for the individual elements in a vector register.

So for instance, they were able to fetch

one data element from here to the vector register,

and another element could be fetched from here.

They were able to do some sort of gather,