ModSy /CoursesID:3914
- Most recent entry on 2024-04-24
Keywords: Simulation Synthese abstraktion vhdl Hardware Description Language Verilog Digital Design Digitalentwurf Hardware-Beschreibungssprache Entity

Lecturer

Dipl.-Ing. Jürgen Frickel

Organisational Unit

Friedrich-Alexander-Universität Erlangen-Nürnberg

Recording type

Übung / Tafelübung

Via

Studon

Language

German

Modelling and Synthesis of Digital Systems

Associated Clips

Episode
Title
Lecturer
Updated
Via
Duration
Media
1
ModSy Lab-1 preview image
ModSy Lab-1
Dipl.-Ing. Jürgen Frickel
2024-04-24
Studon
00:17:18
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