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Thank you so much, Professor Teck, for the kind introduction.

It's my pleasure to be here. In fact, I have just known Professor Jürgen for many years,

and then I also followed the research from this university, this lab,

and also the collection of three universities' collaborative effort in the last few years.

I think there's a lot of overlap, a common interest. I hope to get good feedbacks after this to have the discussion.

This talk was also part of my keynote speech last year at the SOCC conference.

Some of you may submit a paper there, the System on Chip conference.

It turned out to be a 10-year anniversary today, at least this month, for this paper we published in SOCC 2006.

The title was Platform-Based Behavioral System Level Synthesis,

where we outlined at that time, 10 years ago, the research effort, UCLA,

that we can start from C, C++, System C, and with user constraint,

we all the way generate the VHDL bar log for FPGA or ASIC designs.

So that's exactly called the high-level synthesis. We go through multiple steps,

called the compilation, elaboration, and then various kind of transformations at the intermediate representation level,

and then finally the behavior and communication optimization.

So you can see the first two steps are actually very similar to traditional compilation optimization,

except from the intermediate representation, instead of going to RISC processors, X86 processors,

we go directly to hardware implementation.

So that was the research project called the X-Pilot, that was in the paper.

And then, towards the end of the year, we also spin off the company called AutoESL, making this a commercial product.

We were having lunch discussing about why the professor wants to start a company.

The reasons are very simple. When you have a successful research project, and then there's a bunch of companies that want to use it,

it's very hard for us, I believe it's the same thing here, it's very difficult for you to support that out of a research lab,

because they want the bug fixes, feature enhancement, and all of those, right?

And we keep working on new things. The students will graduate, then we'll have new students coming in, different topic.

So the best way to support them is actually to spin off a company, and so they've got a constant, continuous support.

This has been a pattern from my lab. Not every project that we go to this stage, I told students,

for example, we did some very early work on 3D IC designs, 2002, the 3D IC still not come true yet, right?

So if you start a company right after the student graduates, they will be starving by now.

But some of the projects, clearly, you show the promised impact.

So then 2011, Zalinks acquired a company, and so now this is the product, probably many people in the lab have used that,

because I saw multiple publications, Vivado, HLS, they started with called AutoESL.

So there's a number of things that makes this product successful, I will come back to later on.

Maybe it's not necessary for this group, but many people asked the question when they saw the slides,

does it really work? Because they got an impression the high-level synthesis has been tried by many researchers for almost 20, 30 years.

Their experiences was not quite competitive. So in fact, what we have shown is that you can make it very competitive.

Obviously, Zalinks spent a lot of money acquiring the company before they did that.

They did a very careful due diligence internally.

They also hired a company called the Berkeley Design Automation BDTI to do an independent evaluation.

And after that, they wrote a report to their executive committee saying, yeah, we should acquire this company.

So they allow us to publish some of this evaluation data, which was all in this keynote paper in TCAT April 2011.

So, for example, this is one design they were doing for the evaluation of wireless memo sphere decoder.

The reason they chose that is because they have a library team did a good manual RQL design.

So that was a good reference point. At that time, this is about a 4,000 line of C code and targeted for Vertex 5 IPGA.

So this is a successful case where, in fact, the tool performs very well.

You can see in the last registers DSP embedded BRAMs, there's a consistent reduction from 10% all the way to 30%.

So this gives them the confidence that for complex designs, really high level things can be as competitive as a manual design.

In some cases, can even be better.

So that was the BDTI. They had a separate company doing that.