The following content has been provided by the University of Erlangen-Nürnberg.

Good morning everybody, welcome to our today's Invasive Computing Seminar Series.

It's my great pleasure to welcome Dr. Suradip Sarkar.

He has studied and got a Master's Science and PhD degree from Washington State University in the United States.

And since 2011, he is a postdoctoral researcher at Intel's Exa Science Labs at IMAC in Belgium,

and working jointly together with the Ghent University.

His special interests and research interests in general are NOC, NOC design, SOC design, reconfigured systems, and high-performance computing.

We met, that was the point, at the ACASES summer school and found very interesting points of common research interests.

That's why you are here and I'm very glad you took the occasion to visit us here in Erlangen. Please, Suradip.

Thank you Dr. Tai for the introduction, and it's my pleasure to be here.

Today's talk I'll be mostly presenting the work that I was focusing on during my doctoral research,

and towards the end I'll sum it up with the work that I'm doing right now at Exa Science Labs.

So I named the talk, that's why, like large-scale multiprocessing from NOCs basically, which was my previous research topic,

to currently it's like for exascale systems, which is ideally supercomputing systems.

The outline would be as follows, a brief motivation building up with some introduction about NOCs, applications in that domain,

followed by the applications which I had considered during my research, namely biocomputing applications, computational biology.

So this alignment and phylogenetics are two such applications which I picked up, and I'd conclude with that and the first part.

So basically this would be ending with my PhD doctoral research stuff, and then I'd move on to my power-aware multi-core simulation work.

So as scientific applications or the computer architecture community is basically being driven by scientific applications,

I was typically interested in what really is driving or who is driving basically, whether it is the data or just the computational overhead.

What we initially see is that after the 90s, it's been a lot of explosion in just the raw amount of data that is being generated,

like be it computational biology, be it computational chemistry, be it astrophysics, different.

So data explosion is something which the community is really getting to witness.

And the next being, in order to understand this data or process this data well, we need to do some kind of meaningful computation on it.

But some applications are more data intensive, while the other ones are more computer intensive, the amount of data is limited.

So basically whether it's either bandwidth coming into an issue or sometimes it's just the raw computation,

the computational course capability that is really called into the question.

So, but finally what we really understand is we need an underlying computing architecture in order to facilitate or help us in tackling these issues arising out of that.

So one such example, these are some of, sorry.

So some of the scientific applications currently like really driving the explosion of data.

On the right, I have just shown you the GenBank database, which you can clearly see that beyond 1998,

the explosion in just the amount of sequences, the base pairs which sequences which computational biology is typically used, it has really gone up.

Like, and with the state of the, this has gone up because of the advances in sequencing methodologies.

That really, and also sequencing has become a lot cheaper than it used to be in the 90s.

So that has really gone up, but the way in which that data was being processed in using the traditional coarse-grained approaches

are unable to keep pace with this.

So looking into the underlying infrastructure that we need for processing this data,

as we know from our architecture knowledge that clock frequencies are no longer scaling because of thermal and power constraints.

And also that led the community towards more parallelism that, okay, we need to get the Moore's law going.

And the only way we can increase the throughput is by having things done more in parallel.

Some examples being like initially we had the basic core with the control cache and the ALUs,

which finally led to like co-processors, systems, like GPUs where we had a lot of ALU units

and like very simple control, I would say, compared to the superscalar cores.

And nowadays like the whole community is driving towards this, which the figure on the bottom is that of the Intel's ninth ferry, the 32 core mic architecture.

So what the community is going towards is very modular tile-based architecture, having a very high rate of parallelism.

But we are not going for a high clock frequency, basically, in order to keep the thing within the power envelope.

Network on chip, basically because of this demand for increased integration,

network on chip was one such solution which the community looked at and the designers looked at basically abstracting away the communication from that of the core designer.

Like different IP vendors like ARM, also like dedicated video processing, dedicated memory makers, they are designing their IPs individually.

But when we need to integrate onto a single SoC, that infrastructure design should not consume a lot of time or it should be very scalable as the system size increases.