17 - NHR PerfLab Seminar 2021-05-04: Automatic Generation of Models of Microarchtectures/ClipID:32265 previous clip next clip

Keywords: HPC

Recording date 2021-05-04



Organisational Unit

Zentrum für Nationales Hochleistungsrechnen Erlangen (NHR@FAU)


Zentrum für Nationales Hochleistungsrechnen Erlangen (NHR@FAU)

Speaker: Andreas Abel from Saarland University

Title: Automatic Generation of Models of Microarchitectures


Detailed microarchitectural models are necessary to predict, explain, or optimize the performance of software running on modern microprocessors. Building such models often requires a significant manual effort, as the documentation provided by hardware manufacturers is typically not precise enough. In this talk, we will look at techniques for generating models of microarchitectures automatically.

First, I will present nanoBench (https://github.com/andreas-abel/nanoBench), which is a tool for evaluating small microbenchmarks using hardware performance counters on Intel and AMD x86 systems. Unlike previous tools, nanoBench can execute microbenchmarks directly in kernel space. This makes it possible to benchmark privileged instructions, and it enables more accurate measurements. The reading of the performance counters is implemented with minimal overhead, avoiding functions calls and branches.

In the second part of the talk, I will describe techniques to automatically generate microbenchmarks for characterizing cache architectures and for determining the latency, throughput, and port usage of more than 13,000 instruction variants.  We have applied these techniques to 19 different Intel and AMD microarchitectures; the results are available on our website https://www.uops.info.

Date and time: Tuesday, May 4, 2021, 2 p.m.. – 3 p.m.

Short Bio:

Dr. Andreas Abel is a a postdoc at Saarland University in the group of Prof. Jan Reineke. His research interests include reverse engineering of microarchitectures, performance prediction, and security. He completed his PhD in June 2020 with a thesis entitled Automatic Generation of Models of Microarchitectures.

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